The present invention relates to apparatus and method for converting serial bit streams into parallel bit streams and visa versa.
In many electronic systems, digital data must be transferred over a digital bus at a fixed rate (i.e., isochronous) between devices. These digital buses include a clock, synchronization signal and the data. The clock rate is fixed and both the synchronization signal and data are measured relative to it. On a serial TDM bus, the data is transferred one bit at a time (either MSB or LSB first) and the synchronization signal is used to mark the start of the data word. On a parallel TDM bus, all of the bits of the data are transferred at the same time. In the latter case, the synchronization signal is superfluous.
Time Division Multiplexing (TDM) is a known technique for combining N isochronous streams of digital data operating at the same frequency into one isochronous stream of data that operates at a new frequency M equal to N times the original frequency. The synchronization pulses still occur at the original frequency. The combined data transferred between synchronization pulses is called a frame. Each frame is broken into N equally sized pieces called time-slots. Each of the original streams are allotted one of the N time-slots per frame to transfer data. Each stream uses the same time-slot during each frame. As an example, the ST-Bus(trademark) defined by Mitel Semiconductor(trademark) uses a clock rate of 2.048 Mbits/second, 4.096 Mbits/second, or 8.192 Mbits/second with a frame rate of 8 kHz to combine 32, 64, or 128 64-Kbits/second serial streams into one stream.
In general, serial TDM buses have been used in favor of parallel TDM buses because serial TDM buses require fewer connections between devices. However, it is common to see multiple serial TDM streams running in parallel to achieve increased bandwidth (e.g., MVIP, SCSA, and H.110 computer telephony buses). These multiple streams are often referred to as a TDM highway.
In systems using multiple serial streams it becomes necessary to create a digital switch that is capable of transmitting data from a time-slot on one stream onto either a different timeslot on the same stream or onto another stream altogether. As the number of serial TDM streams increases, these switching devices usually convert the serial TDM streams into a parallel TDM stream internally to the device. This makes it easier to store the data in memory.
If the data on the streams is to be processed by a computer, again the data must be converted from serial to parallel form. Often a single stream serial-to-parallel converter is incorporated into the computer. The serial port is connected to a switching device and other streams are then connected to the TDM highway.
These two concepts can be combined so that data taken from the TDM highway is converted to parallel and stored in a memory device (e.g., a RAM). for use by the processor. The processor also places data to be transmitted on the TDM highway into the memory device, and the circuit converts this data from parallel to serial.
FIG. 1 illustrates a block diagram of a prior art parallel-to-serial/serial-to-parallel conversion engine 18 for connecting to a serial stream. Each timeslot may be either driven from this circuit or received from a different circuit. The (tri-state) buffers illustrate that the same wires are used for input and output. The mechanism by which data is moved from the parallel stream into (and out of) the holding register as well as the control circuit for the tri-state buffers is not covered in this document.
The shift registers are clocked at the bit rate of the serial stream (e.g., 8.192 MHz), however there is usually a phase shift of either 180xc2x0or 270xc2x0between the outgoing and incoming clocks. At the timeslot boundary the outgoing data is moved from the output holding register to the output shift register. At the same time, the incoming data is moved from the input shift register to the input holding register. The data in the shift registers is corrupted after only one bit-slot without the use of the holding registers. This is generally not enough time to move the data from multiple serial streams onto the parallel bus.
Referring still to FIG. 1, thirty-two flip-flops are used per serial stream. Therefore, 1024 flip-flops are necessary in this embodiment to support the thirty-two streams of the H.100/H.110 bus. Significantly, all thirty-two output holding registers are unloaded and all thirty-two input holding registers are loaded at the same time causing an undesirably large amount of power to dissipate at one instant. In addition, a large decoder and multiplexor is required to move data to and from the holding registers.
An improved technique is disclosed in U.S. Pat. 4,924,464 entitled xe2x80x9cTechnique for Converting Either Way Between a Plurality of N Synchronized Serial Bit Streams and a Parallel IDM Formatxe2x80x9d. This patent discloses the use of a two dimensional barrel shifter to implement the parallel-to-serial and serial-to-parallel conversions. Notably, this technique uses half of the number of flip-flops in comparison to the prior art system illustrated in FIG. 1. However, the system disclosed in this U.S. patent requires a large number of interconnects between flip-flops, and again all of the flip-flops are loaded on each clock edge causing a relatively large amount of power to dissipate at the same time.
Therefore, there is a need for an improved serial-to-parallel and parallel-to-serial converter.
Briefly, according to a first aspect of the present invention, a serial-to-parallel data conversion device receives a serially received data word and provides a parallel output data word. The conversion engine includes a serial data input interface that receives the serially received data word and provides a received data word. A serial-to-parallel mapping circuit receives the received data word and generates memory write control and write address signals. A memory device includes a first port responsive to the memory write control signals and write address signals for writing the received data word into the memory device, and a second port responsive to memory read control and read address signals for reading data from the memory device. Output interface circuitry generates the memory read control and read address signals, and receives output data from the memory device and reorders the bits of the parallel output data to provide the parallel data word.
According to another aspect of the present invention, a parallel-to-serial conversion device receives a parallel received data word and provides a serial data word. The parallel-to-serial conversion device includes a memory device having a first port responsive to memory write control and write address signals, and a second port responsive to memory read control and read address signals. A parallel-to-serial mapping circuit receives the parallel received data word and generates the memory write control and write address signals to write a bit shuffled version of the parallel received data word into the memory device. A data output interface generates the memory read control and read address signals to perform reads from the memory device and receives output data from the memory device to provide the serial data word.
The conversion engines of the present invention provide a bi-directional interface between a serial TDM highway and a parallel TDM highway.
Advantageously, the present invention uses significantly fewer transistors and consumes significantly less power than earlier implementation. The amount of the savings increases as the number of streams in the serial TDM highway increases.
These and other objects, features and advantages of the present invention will become apparent in light of the following detailed description of preferred embodiments thereof, as illustrated in the accompanying drawings.